UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 85

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
To prevent the WDT from timing out and generating a reset, firmware must repeatedly write
some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the
upper 8 bits of the 24-bit counter are loaded with the written value, and the lower 16 bits of
the counter are cleared to 0000h.
The WDT time-out period can be adjusted by writing a value other that 00h to WDRST. For
example, if WDRST is written with 04h, then the WDT will start counting 040000h, 040001h,
040002h, and so on for each MCU machine cycle. In this example, the WDT time-out period
is shorter than if WDRST was written with 00h, because the WDT is an up-counter. A value
for WDRST should never be written that results in a WDT time-out period shorter than the
time required to complete the longest code task in the application, else unwanted WDT
overflows will occur.
Figure 24. Watchdog counter
The formula to determine WDT time-out period is:
WDT
N
determined by the value written to the SFR, WDRST.
t
cycle is always 4 MCU_CLK periods for uPSD34xx, but the following factors can sometimes
add more MCU_CLK periods per machine cycle:
●
●
t
is fixed by the following factors:
●
●
As an example, assume the following:
1.
2.
3.
4.
5.
MACH_CYC
MACH_CYC
OVERFLOW
23
The number of MCU_CLK periods assigned to MCU memory bus cycles as determined
in the SFR, BUSCON. If this setting is greater than 4, then machine cycles have
additional MCU_CLK periods during memory transfers.
Whether or not the PFQ/BC circuitry issues a stall during a particular MCU machine
cycle. A stall adds more MCU_CLK periods to a machine cycle until the stall is
removed.
Frequency of the external crystal, resonator, or oscillator: (f
Bit settings in the SFR CCON0, which can divide f
f
CCON0 is 10h, meaning no clock division, so the period of MCU_CLK is also 25ns.
BUSCON is C1h, meaning the PFQ and BC are enabled, and each MCU memory bus
cycle is 4 MCU_CLK periods, adding no additional MCU_CLK periods to MCU machine
cycles during memory transfers.
Assume there are no stalls from the PFQ/BC. In reality, there are occational stalls but
their occurance has minimal impact on WDT timeout period.
WDRST contains 00h, meaning a full 2
generate a reset.
PERIOD
OSC
is 40MHz, thus its period is 25ns.
is the average duration of one MCU machine cycle. By default, an MCU machine
is also affected by the absolute time of a single MCU_CLK period. This number
SFR, WDRST
is the number of WDT up-counts required to reach FFFFFFh. This is
= t
8-bits
MACH_CYC
x N
OVERFLOW
15
8-bits
24
up-counts are required to reach FFFFFh and
OSC
and change MCU_CLK
7
OSC
Supervisory functions
)
8-bits
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