C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 119

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

Comparator interrupts can be generated on either rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see
falling -edge interrupts are enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits (CPn-
RIE and CPnFIE) in their respective Comparator Mode Selection Register (CPTnMD), shown in
Figure 12.4. These bits allow the user to control which edge (or both) will cause a comparator interrupt.
However, the comparator interrupt must also be enabled in the Extended Interrupt Enable Register (EIE1).
The CPnFIF flag is set to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge interrupt. Once set, these bits remain set until cleared by soft-
ware. The output state of a Comparator can be obtained at any time by reading the CPnOUT bit. A Com-
parator is enabled by setting its respective CPnEN bit to logic 1, and is disabled by clearing this bit to logic
0.Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a com-
parator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up
time” as specified in Table 12.1, “Comparator Electrical Characteristics,” on page 122.
12.1. Comparator Inputs
The Port pins selected as comparator inputs should be configured as analog inputs in the Port 2 Input Con-
figuration Register (for details on Port configuration, see
Inputs” on page
207). The inputs for Comparator are on Port 2 as follows:
Comparator Input
CP0 +
CP1 +
CP2 +
CP0 -
CP1 -
CP2 -
Section “13.3. Interrupt Handler” on page
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Section “18.1.3. Configuring Port Pins as Digital
Port PIN
P2.6
P2.7
P2.2
P2.3
P2.4
P2.5
151). The rising and/or
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