C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 164

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

C8051F060/1/2/3/4/5/6/7
14.1. Power-on Reset
The C8051F060/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset
state until VDD rises above the V
to Table 14.1 for the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted
low until the end of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize. The VDD
Monitor reset is enabled and disabled using the external VDD monitor enable pin (MONEN).
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag
to determine if a power-up was the cause of reset. The contents of internal data memory should be
assumed to be undefined after a power-on reset.
14.2. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below V
monitor will drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see
Figure 14.2). Note that even though internal data memory contents are not altered by the power-fail reset,
it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag
is set to logic 1, the data may no longer be valid.
14.3. External Reset
The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting
the /RST pin low will cause the MCU to enter the reset state. It may be desirable to provide an external
pull-up and/or decoupling of the /RST pin to avoid erroneous noise-induced resets. The MCU will remain in
164
Logic HIGH
Logic LOW
2.70
2.55
2.0
1.0
/RST
V
RST
RST
level during power-up. See Figure 14.2 for timing diagram, and refer
Figure 14.2. Reset Timing
Power-On Reset
100ms
Rev. 1.2
VDD Monitor Reset
100ms
RST
, the power supply
t