C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 138

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

C8051F060/1/2/3/4/5/6/7
On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE
register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as
it did prior to the interrupts occurring. See Figure 13.8 below.
Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE,
SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is
possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct
access to the SFR Page stack can be useful to enable real-time operating systems to control and manage
context switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See Figure 13.9.
138
Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt
SFRNEXT
SFRPAGE
popped to
stack on return from
popped off of the
SFR Page 0x02
(Port 5)
Automatically
0x0F
interrupt
Rev. 1.2
SFRPAGE
SFRNEXT
SFRLAST