C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 323

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

This register determines how the Flash interface logic will respond to reads and writes to the
FLASHDAT Register.
Bit7:
Bits6-4:
Bits3-0:
SFLE
Bit7
SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes through the JTAG port are directed to the 128-
byte Scratchpad Flash sector. When SFLE is set to logic 1, Flash accesses out of the
address range 0x00-0x7F should not be attempted. Reads/Writes out of this range will yield
undefined results.
0: Flash access from JTAG directed to the Program/Data Flash sector.
1: Flash access from JTAG directed to the Scratchpad sector.
WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000:
ignored.
001:
FLASHADR register. FLASHADR is incremented by one when complete.
010:
containing the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x7BFE - 0x7BFF, the entire user space will be
erased (i.e. entire Flash memory except for Reserved area 0x7C00 - 0x7FFF).
(All other values for WRMD2-0 are reserved.)
RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000:
ignored.
0001:
if no operation is currently active. This mode is used for block reads.
0010:
operation is active and any data from a previous read has already been read from FLASH-
DAT. This mode allows single bytes to be read (or the last byte of a block) without initiating
an extra read.
(All other values for RDMD3-0 are reserved.)
WRMD2
Bit6
A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
Figure 26.3. FLASHCON: JTAG Flash Control Register
WRMD1
Bit5
WRMD0
Bit4
Rev. 1.2
RDMD3
Bit3
C8051F060/1/2/3/4/5/6/7
RDMD2
Bit2
RDMD1
Bit1
RDMD0
Bit0
Reset Value
00000000
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