C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 264

MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP

C8051F066-GQ

Manufacturer Part Number
C8051F066-GQ
Description
MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Datasheets

Specifications of C8051F066-GQ

Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
59
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
2-chx16-bit
Number Of Timers
5
Ram Size
4.25 KB
Program Memory Size
32 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1221

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F066-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F066-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F060/1/2/3/4/5/6/7
264
Parameter
Master Mode Timing
T
T
T
T
Slave Mode Timing
T
T
T
T
T
T
T
T
T
T
T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
SYSCLK
is equal to one period of the device system clock (SYSCLK).
Description
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
(See Figure 21.14 and Figure 21.15)
(See Figure 21.12 and Figure 21.13)
Table 21.1. SPI Slave Timing Parameters
Rev. 1.2
1*T
1*T
1*T
2*T
2*T
5*T
5*T
2*T
2*T
6*T
SYSCLK
Min
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
20
0
+
4*T
4*T
4*T
8*T
Max
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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