C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 272

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

C8051F060/1/2/3/4/5/6/7
address as valid. If a master were to then send an address of “11111111”, all three slave devices would rec-
ognize the address as a valid broadcast address.
22.3. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the
SBUF0 register while a transmit is in progress. Note that the TXCOL0 bit is also used as the SM20 bit
when written by user software. This bit does not generate an interrupt.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive
buffer before software has read the previous byte. Note that the RXOV0 bit is also used as the SM10 bit
when written by user software. The Frame Error bit (FE0 in register SSTA0) reads ‘1’ if an invalid (low)
STOP bit is detected. Note that the FE0 bit is also used as the SM00 bit when written by user software.
The RXOV0 and FE0 bits do not generate interrupts.
272
RX
Master
Device
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
Rev. 1.2
RX
Device
Slave
TX
RX
Device
Slave
TX
+5V