C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 215

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

Bits7-0:
Note:
Bits7-0:
P1.7
R/W
R/W
Bit7
Bit7
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
On the C8051F060/1/2/3, P1.[7:0] can be configured as inputs to ADC2 as AIN2.[7:0], in
which case they are ‘skipped’ by the Crossbar assignment process and their digital input
paths are disabled, depending on P1MDIN (See Figure 18.12). Note that in analog mode,
the output mode of the pin is determined by the Port 1 latch and P1MDOUT (Figure 18.13).
See
about ADC2.
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. The state of the weak pull-up is determined by the WEAKPUD bit (XBR2.7,
see Figure 18.7).
Section “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page 87
P1.6
R/W
R/W
Bit6
Bit6
Figure 18.12. P1MDIN: Port1 Input Mode Register
P1.5
R/W
R/W
Bit5
Bit5
Figure 18.11. P1: Port1 Data Register
P1.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P1.3
R/W
R/W
Bit3
Bit3
C8051F060/1/2/3/4/5/6/7
P1.2
R/W
R/W
Bit2
Bit2
P1.1
R/W
R/W
Bit1
Bit1
for more information
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P1.0
R/W
R/W
Bit0
Bit0
0x90
All Pages
0xAD
F
Addressable
Reset Value
Reset Value
11111111
11111111
Bit
215