C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 275

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

Bit7:
Bit6:
Bit5:
Bit4:
Bits3-2:
Bits1-0:
†
Note: FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions.
FE0
R/W
Bit7
FE0: Frame Error Flag.
This flag indicates if an invalid (low) STOP bit is detected.
0: Frame Error has not been detected.
1: Frame Error has been detected.
RXOV0: Receive Overrun Flag.
This flag indicates new data has been latched into the receive buffer before software has
read the previous byte.
0: Receive overrun has not been detected.
1: Receive Overrun has been detected.
TXCOL0: Transmit Collision Flag.
This flag indicates user software has written to the SBUF0 register while a transmission is in
progress.
0: Transmission Collision has not been detected.
1: Transmission Collision has been detected.
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for config-
urations described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
UART0 Transmit Baud Rate Clock Selection Bits.
UART0 Receive Baud Rate Clock Selection Bits.
S0RCLK1 S0RCLK0
S0TCLK1
RXOV0
R/W
Bit6
0
0
1
1
0
0
1
1
Figure 22.9. SSTA0: UART0 Status and Clock Selection Register
TXCOL0
S0TCLK0
R/W
Bit5
0
1
0
1
0
1
0
1
†
SMOD0
R/W
Bit4
Timer 2 Overflow generates UART0 RX baud rate
Timer 3 Overflow generates UART0 RX baud rate
Timer 4 Overflow generates UART0 RX baud rate
Timer 2 Overflow generates UART0 TX baud rate
Timer 3 Overflow generates UART0 TX baud rate
Timer 4 Overflow generates UART0 TX baud rate
Serial Transmit Baud Rate Clock Source
Serial Receive Baud Rate Clock Source
Timer 1 generates UART0 RX Baud Rate
Timer 1 generates UART0 TX Baud Rate
†
S0TCLK1 S0TCLK0 S0RCLK1
†
R/W
Bit3
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
R/W
Bit1
SFR Address:
S0RCLK0
SFR Page:
R/W
Bit0
0x91
0
Reset Value
00000000
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