C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 299

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

Bit7:
Bit6:
Bit5-4:
Bit3:
Bit2:
Bit1:
Bit0:
SFR Address: TMR2CN: 0xC8; TMR3CN: 0xC8; TMR4CN: 0xC8
SFR Page: TMR2CN: page 0; TMR3CN: page 1; TMR4CN: page 2
R/W
TFn
Bit7
TFn: Timer 2, 3, and 4 Overflow/Underflow Flag.
Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from
the value placed in RCAPnH:RCAPnL to 0XFFFF (in Auto-reload Mode), or underflows from
0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
EXFn: Timer 2, 3, and 4 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit
causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
Reserved.
EXENn: Timer 2, 3, and 4 External Enable.
Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direc-
tion of the timer/counter (up or down count). If DCENn = 1, TnEX will determine if the timer
counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as
a digital input.
0: Transitions on the TnEX pin are ignored.
1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count
(up or down) as follows:
Capture Mode: ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer
value.
Auto-Reload Mode:
TRn: Timer 2, 3, and 4 Run Control.
This bit enables/disables the respective Timer.
0: Timer disabled.
1: Timer enabled and running/counting.
C/Tn: Counter/Timer Select.
0: Timer Function: Timer incremented by clock defined by TnM1:TnM0
(TMRnCF.4:TMRnCF.3).
1: Counter Function: Timer incremented by high-to-low transitions on external input pin.
CP/RLn: Capture/Reload Select.
This bit selects whether the Timer functions in capture or auto-reload mode.
0: Timer is in Auto-Reload Mode.
1: Timer is in Capture Mode.
EXFn
R/W
Bit6
DCENn = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag.
DCENn = 1: TnEX logic level controls direction of timer (up or down).
Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.2
EXENn
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
TRn
R/W
Bit2
C/Tn
R/W
Bit1
CP/RLn
R/W
Bit0
Addressable
Reset Value
00000000
Bit
299