C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet - Page 319

• Manufacturer Part Number: C8051F066-GQ
• Description: MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F066-GQ

• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 59
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 2-chx16-bit
• Number Of Timers: 5
• Ram Size: 4.25 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1221

EXTEST provides access to both capture and update actions, while Sample only performs a capture.
102, 104, 106, 108
103, 105, 107, 109
110, 112, 114, 116,
118, 120, 122, 124
111, 113, 115, 117,
119, 121, 123, 125
79, 81, 83, 85, 87,
94, 96, 98, 100,
95, 97, 99, 101,
89, 91, 93
Bit
Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6) (Continued)
Action
Capture P5.n input from pin (follows P0.n numbering scheme)
Update
Capture P6.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P6.n input from pin (follows P0.n numbering scheme)
Update
Capture P7.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P7.n input from pin (follows P0.n numbering scheme)
Update
Target
P5.n output to pin (follows P0.n numbering scheme)
P6.n output enable to pin (follows P0.n numbering scheme)
P6.n output to pin (follows P0.n numbering scheme)
P7.n output enable to pin (follows P0.n numbering scheme)
P7.n output to pin (follows P0.n numbering scheme)
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
319