FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 103

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Command/Data
ECP Mode supports two advanced features to
improve the effectiveness of the protocol for some
applications. The features are implemented by
allowing the transfer of normal 8 bit data or 8 bit
commands.
When in the forward direction, normal data is
transferred when HostAck is high and an 8 bit
command is transferred when HostAck is low.
The most significant bit of the command indicates
whether it is a run-length count (for compression)
or a channel address.
When in the reverse direction, normal data is
transferred when PeriphAck is high and an 8 bit
command is transferred when PeriphAck is low.
The most significant bit of the command is always
zero. Reverse channel addresses are seldom
used and may not be supported in hardware.
Data Compression
The ECP port supports run length encoded (RLE)
decompression in hardware and can transfer
compressed data to a peripheral. Run length
encoded (RLE) compression in hardware is not
supported. To transfer compressed data in ECP
mode, the compression count is written to the
ecpAFifo and the data byte is written to the
ecpDFifo.
Compression
identical bytes and transmitting an RLE byte that
indicates how many times the next byte is to be
repeated. Decompression simply intercepts the
RLE byte and repeats the following byte the
specified number of times. When a run-length
count
Reverse Channel Commands (PeripAck Low)
Forward Channel Commands (HostAck Low)
D7
0
1
is
Run-Length Count (0-127)
0011 0X00 only)
Channel Address (0-127)
received
is
TABLE 44 -
accomplished
from
D[6:0]
a
peripheral,
by
(mode
counting
the
103
subsequent data byte is replicated the specified
number of times. A run-length count of zero
specifies that only one byte of data is represented
by the next data byte, whereas a run-length count
of 127 indicates that the next byte should be
expanded to 128 bytes. To prevent data
expansion, however, run-length counts of zero
should be avoided.
Pin Definition
The drivers for nStrobe, nAutoFd, nInit and
nSelectIn are open-collector in mode 000 and are
push-pull in all other modes.
ISA Connections
The interface can never stall causing the host to
hang. The width of data transfers is strictly
controlled on an I/O address basis per this
specification. All FIFO-DMA transfers are byte
wide, byte aligned and end on a byte boundary.
(The PWord value can be obtained by reading
Configuration Register A, cnfgA, described in the
next section).
always possible with standard or PS/2 mode using
program control of the control signals.
Interrupts
The interrupts are enabled by serviceIntr in the ecr
register.
serviceIntr = 1 Disables the DMA and all of the
serviceIntr = 0
Single byte wide transfers are
service interrupts.
condition.
condition is valid, then the
interrupt
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO
threshold.
Enables the selected interrupt
does
If the interrupting
is
not
cross
generated
the