FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 93

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
PDIR
SIGNAL
EPP
For correct EPP read cycles, PCD is required to be a low.
Address/Data
nWait
nData Strobe
nReset
Parallel Port
nWrite
Interrupt
nAddress
Strobe
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Status
Error
Direction
EPP NAME
TABLE 39 - EPP PIN DESCRIPTIONS
TYPE
I/O
O
O
O
O
O
I
I
I
I
I
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low.
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and a
high means an input/read condition. This signal is normally a
low (output/write) unless PCD of the control register is set or if
an EPP read cycle is in progress.
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EPP DESCRIPTION
It is driven inactive as a positive