FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 117

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

therefore only the Host controller can initiate
the
continuously sample the Stop Frames pulse
width to determine the next IRQSER Cycle’s
mode.
IRQSER Data Frame
Once a Start Frame has been initiated, the
FDC37B72x will watch for the rising edge of the
Start Pulse and start counting IRQ/Data Frames
from there.
clocks: Sample phase, Recovery phase, and
Turn-around phase. During the Sample phase
the FDC37B72x must drive the IRQSER (SIRQ
pin) low, if and only if, its last detected IRQ/Data
value was low. If its detected IRQ/Data value is
high, IRQSER must be left tri-stated. During the
first
IRQSER PERIOD
Start
Each IRQ/Data Frame is three
10
11
12
13
14
15
16
Frame.
1
2
3
4
5
6
7
8
9
Slaves
IRQSER Sampling Periods
SIGNAL SAMPLED
must
nSMI/IRQ2
Not Used
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
117
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
Recovery phase the FDC37B72x must drive the
SERIRQ high, if and only if, it had driven the
IRQSER low during the previous Sample Phase.
During the Turn-around Phase the FDC37B72x
must tri-state the SERIRQ. The FDC37B72x will
drive the IRQSER line low at the appropriate
sample point if its associated IRQ/Data line is
low, regardless of which device initiated the Start
Frame.
The Sample Phase for each IRQ/Data follows the
low to high transition of the Start Frame pulse by
a number of clocks equal to the IRQ/Data Frame
times three, minus one. (e.g. The IRQ5 Sample
clock is the sixth IRQ/Data Frame, (6 x 3) - 1 =
17th clock after the rising edge of the Start
Pulse).
# OF CLOCKS PAST START
11
14
17
20
23
26
29
32
35
38
41
44
47
2
5
8