FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 137

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 1: All soft power management functions run off of VTR. When VTR is not present, Vbat supplies
Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine.
Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 to come
REGISTERS
Button Input
A transition on the Button input, or on any enabled
A low pulse on the Soft Power Off signal, a Vbat POR, a VTR POR with Vbat<1.2V, or Power Button Override Event causes
nPowerOn to float.
ED;PG = Edge Detect, Pulse Generator
ED;L = Edge Detect and Latch
power to Flip Flop 1.
up ‘off’ after a VTR POR, the VTR_POR_OFF bit. A similar bit can be set to force Flip Flop 1 to
come up ‘on’ after a VTR POR, the VTR_POR_EN bit. These bits are in the Soft Power Enable
Register 2 in Logical Device 8 at 0xB1, defined as follows.
Bit 4 – VTR_POR_OFF
If VTR_POR_OFF is set, the nPowerOn pin will go inactive (float) and the main power (Vcc) will
remain off when the VTR POR occurs.
VTR_POR_EN at the same time.
BIT 6 - VTR_POR_EN
If VTR_POR_EN is set, the nPowerOn pin will go active (low) and the machine will power-up as
soon as a VTR POR occurs. The software must not set VTR_POR_OFF and VTR_POR_EN at
the same time.
SP1
SPx
FIGURE 5 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM
L
nSPOFF1
nSPOFF1
Button
ENx
EN1
ED; L
ED; L
ED; PG
OFF_EN
OFF_DLY
PWRBTNOR_EN
SPx
inputs causes the nPowerOn output to go active low.
Delay2
nSPOFF
137
The software must not set VTR_POR_OFF and
VTR_POR_EN
Override
AL_REM_EN
Timer
VTR POR
Soft Power
Off
V
Vbat<1.2V
V
Logic
TR
BAT
Alarm
V
nSPOFF1
TR_
POR With
POR
VTR POR
POR_OFF
PWRBTNOR_STS
Logic
Logic
VTR
nSPOFF1
Flop 1
D
CLR
Flip
Q
Delay1
OFF_DLY
nBINT
Type Output
Open Collector
nPowerOn