FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 149

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Power Management 1 Control Register 2 (PM1_CNTRL 2)
Register Location:
Default Value:
Attribute:
Size:
0
1
2-4
5
6-7
General Purpose Event Status Register 1 (GPE_STS1)
Register Location:
Default Value:
Attribute:
Size:
0
1-7
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position
and by Vbat POR. Writing a 0 has no effect.
BIT
BIT
Reserved
PWRBTNOR_EN
SLP_TYPx
SLP_EN
Reserved
SCI_STS1
Reserved
NAME
NAME
<PM1_BLK>+5 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+8 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
Reserved. This field always returns zero.
This bit controls the power button over-ride function. When set, then
anytime the Button_In signal is asserted for more than four seconds
the system will transition to the off state. When a power button over-
ride event occurs, the logic clears the PWRBTN_STS bit, and sets
the PWRBTNOR_STS bit.
This 3-bit field defines the type of hardware sleep state the system
enters when the SLP_EN bit is set to one. When this field is 000 the
FDC37B72x will transition the machine to the off state when the
SLP_EN bit is set to one. That is, with this field set to 000, nPowerOn
will go inactive (float) after a 1-2 clock delay when SLP_EN is set.
This delay is a minimum of one 32kHz clock and a maximum of two
32kHz clocks (31.25μsec-62.5μsec). When this field is any other
value, there is no effect.
This is a write-only bit and reads to it always return a zero. Writing ‘1’
to this bit causes the system to sequence into the sleeping state
associated with the SLP_TYPx fields after a 1-2 clock delay, if the
SLP_CTRL bit in the sleep / wake configuration register (0xF0 in
Logical Device A) is cleared. If the SLP_CTRL bit is set, do not
sequence into the sleeping state associated with the SLP_TYPx field,
but generate an SMI. Note: the SLP_EN_SMI bit in the SMI Status
Register 2 is always set upon writing ‘1’ to the SLP_EN bit. Writing ‘0’
to this bit has no effect.
Reserved. This field always returns zero.
This bit is set when the device power management events (PME
events) occur. When enabled, the setting of this bit will generate an
SCI interrupt. (Note 1)
Reserved. These bits always return a value of zero.
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DESCRIPTION
DESCRIPTION