FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 113

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

UART POWER MANAGEMENT
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B4
and B5. When set, these bits allow the following
auto power management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to the
XMIT buffer. The receiver exits auto powerdown
when RXDx changes state.
PARALLEL PORT
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B3.
When set, this bit allows the ECP or EPP logical
parallel port blocks to be placed into powerdown
when not being used.
The EPP logic is in powerdown under any of the
following conditions:
1.
2.
The ECP logic is in powerdown under any of the
following conditions:
The transmitter enters auto powerdown when
the transmit buffer and shift register are
empty.
The receiver enters powerdown when the
following conditions are all met:
A.
B.
EPP is not enabled in the configuration
registers.
EPP is not selected through ecr while in ECP
mode.
Receive FIFO is empty
The receiver is waiting for a start bit.
While in powerdown the Ring Indicator
interrupt is still valid and transitions when
the RI input changes.
113
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
V
This chip requires a (TBD) MicroAmp battery
supply (V
registers. These registers retain the contents of
the general purpose registers and wake-up event
registers.
V
The FDC37B72x requires a 25 mA trickle
(standby) supply (V
for the programmable wake-up events in the Soft
Power Management logic, SCI, PME and SMI
interfaces when V
FDC37B72x is not intended to provide wake-up
capabilities on standby power, V
connected to V
the PME registers, the PME interface, the ACPI
registers, the SCI interface, the GPIO logic, the
GPIO configuration registers and other wakeup
related configuration registers.
generates a V
initialize certain components. All wakeup event
registers and related logic are battery backed-up
to retain the configuration of the wakeup events
upon a power loss (i.e., V
V). These registers are reset on a V
The following section lists the pins that are active
under VTR power.
INTERNAL PWRGOOD
An internal PWRGOOD logical control is included
to minimize the effects of pin-state uncertainty in
the host interface as V
When the internal PWRGOOD signal is “1”
BAT
TR
ECP is not enabled in the configuration
registers.
SPP, PS/2 Parallel port or EPP mode is
selected through ecr while in ECP mode.
Support
Support
BAT
) to provide battery backed up
CC
TR
. V
TR
CC
Power-on-Reset signal to
TR
) to provide sleep current
powers the IR interface,
is removed.
cc
CC
cycles on and off.
= 0 V and V
The V
TR
BAT
can be
TR
If the
TR
POR.
= 0
pin