FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 171

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices.
Interrupt Select Configuration Register
Note:
Note: IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
Interrupt
Request Level
Select 0
Default = 0x00
on Vcc POR or
Reset_Drv
LOGICAL
NUMBER
DEVICE
0x0A
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
for the Serial Port logical device by setting any combination of bits D0-D3 in the IER
and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
for the KYBD by (refer to the KYBD controller section of this spec.)
NAME
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
LOGICAL
DEVICE
ACPI
Table 66 - Interrupt Select Configuration Register Description
0x70 (R/W)
REG INDEX
REGISTER
0x60,0x61
INDEX
Bits[3:0] selects which interrupt level is used for
Interrupt 0.
0x02=IRQ2
0x0E=IRQ14
0x0F=IRQ15
Note: All interrupts are edge high (except ECP/EPP)
•
0x00=no interrupt selected.
0x01=IRQ1
BOUNDARIES
[0x00:0x0FE7]
ON 24 BYTE
BASE I/O
(NOTE3)
•
•
RANGE
172
DEFINITION
BASE OFFSETS
FIXED
STATE
C