FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 227

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note:
NAME
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
t2
t3
t4
t5
t8
WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP
Read.
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PDATA Valid to SDATA Valid
Time Out
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
TABLE 95 - EPP 1.7 DAT OR ADDRESS READ CYCLE TIMING
DESCRIPTION
228
MIN
10
40
10
40
0
0
0
0
0
0
TYP
MAX
50
40
24
50
40
40
12
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns