FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 150

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

General Purpose Event Enable Register 1 (GPE_EN1)
Register Location:
Default Value:
Attribute:
Size:
0
1-7
Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the
register is written.
PME Registers
The power management event function has a PME_Status bit and a PME_En bit. These bits are
defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright ©
1997, PCI Special Interest Group, Mar. 18, 1997.
The default states for the PME_Status and PME_En bits are controlled by V
PME Status Register (PME_STS)
Register Location:
Default Value:
Attribute:
Size:
•
•
•
•
BIT
The PME_Status bit is set when the FDC37B72x would normally assert the PCI nPME signal,
independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can
set the PME_Status bit.
The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it and cause
the FDC37B72x to stop asserting the nPME, if enabled.
Writing a “0” has no effect on the PME_Status bit.
The PME_Status bit is reset to “0” during VBAT Power-On-Reset.
SCI_EN1
Reserved
D7
NAME
D6
D5
<PM1_BLK>+9 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+10h System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
RESERVED
When this bit is set, then the enabled device power management events
(PME events) will generate an SCI interrupt. When this bit is reset,
device power management events will not generate an SCI interrupt.
Reserved. These bits always return a value of zero.
D4
D3
D2
150
D1
DESCRIPTION
PME_Status
D0
bat
Power-On-Reset.
DEFAULT
0x00