FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 123

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

function.
Register determines the port direction, bit[1]
determines the signal polarity, bits[4:3] select the
port function, bit[5] enables the interrupt, and bit[7]
determines the output driver type select. The
GPIO configuration register Output Type select
bit[7] applies to GPIO functions, the Watchdog
Timer WDT, the LED and the nSMI Alternate
functions. The basic GPIO configuration options
are summarized in TABLE 53.
For Alternate functions, the pin direction is set and
controlled internally, regardless of the state
Bit[0] of each GPIO Configuration
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of the GPIO Direction bit[0].
Alternate INPUT functions cannot be inverted,
regardless of the state of the GPIO polarity bit[1],
except for the EETI function.
The interrupt channel for the group Interrupts is
selected
registers defined in the FDC37B72x Configuration
Register Section. The group interrupts are
"ORed" function of the group interrupt enabled
GPIO ports and will represent a standard ISA
interrupt (edge high).
Interrupts can generate SMI events, wake-up
events through the Soft Power Management logic,
and SCI/PME events. See the ACPI, PME and
SMI section for details.
When the group interrupt is enabled on a GPIO
input port, the interrupt circuitry contains a
selectable digital debounce filter so that switches
or push-buttons may be directly connected to the
chip. The debounce filters reject signals with pulse
widths ≤1ms and are enabled per interrupt group
in the GP_INT[2:1] configuration registers.
The state of unconnected GPIO alternate input
functions is inactive. For example, if bits[4:3] in
LD8 -CRCB are not “00”, i.e. nROMCS is not the
selected function for GP53, internally the state of
nROMCS is inactive, “1”.
by
the
GP_INT[2:1]
GPIO Group 1 and 2
Also, selected
configuration
the