FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 231

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been
Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
PDATA<7:0>
NAME
t1
t2
t3
t4
t5
t6
nAUTOFD
nACK
received. ECP can stall by keeping nAUTOFD low.
PDATA Valid to nACK Asserted
nAUTOFD Deasserted to PDATA Changed
nACK Asserted to nAUTOFD Deasserted
(Notes 1,2)
nACK Deasserted to nAUTOFD Asserted (Note 2)
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
FIGURE 30 - ECP PARALLEL PORT REVERSE TIMING
TABLE 98 - ECP PARALLEL PORT REVERSE TIMING
DESCRIPTION
t4
t1
t5
232
t3
t6
MIN
80
80
0
0
0
0
t4
TYP
t2
MAX
200
200
UNITS
ns
ns
ns
ns
ns
ns