FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 151

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

PME Enable Register (PME_EN)
Register Location:
Default Value:
Attribute:
Size:
•
•
•
PME Status Register 1 (PME_STS 1)
Register Location:
Default Value:
Attribute:
Size:
DEVINT_ST
PME Status Register 2 (PME_STS2)
Register Location:
Default Value:
Attribute:
Size:
•
•
PME Enable Register 1 (PME_EN1)
Register Location:
Default Value:
Attribute:
Size:
GP17
DEVINT_EN
D7
Setting the PME_En bit to “1” enables the FDC37B72x to assert the nPME signal.
When the PME_En bit is reset to “0”, nPME signal assertion is disabled.
The PME_En bit is reset to “0” during VBAT Power-On-Reset.
D7
The PME Status registers indicate the state of the individual FDC37B72x PME wake sources,
independent of the state of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Status bit will be “1”. The wake
source bits in the PME Status registers are read/write-clear: an active (“1”) PME Status bit can only
be cleared by writing a “1” to the bit. Writing a “0” to bits in the PME Wake Status register has no
effect.
S
D7
D7
GP16
D6
Reserved
D6
Reserved
D6
D6
GP15
D5
D5
<PM1_BLK>+11h System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+Ch System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+Dh System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+Eh System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
nRING
nRING
RESERVED
D5
D5
D4
GP14
D4
MOUSE
MOUSE
D4
D4
D3
GP13
D3
151
KBD
D3
KBD
D3
D2
GP12
D2
RI1
D2
RI1
D2
D1
GP11
RI2
D1
RI2
D1
D1
PME_En
D0
Reserved
Reserved
GP10
D0
D0
D0
DEFAULT
0x00
DEFAULT
DEFAUL
DEFAULT
0x00
0x00
0x00
T