FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 194

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

WDT_CFG
Default = 0x00
On VTR POR
Bits[0,2-7] are also
cleared on V
or RESET_DRV
WDT_CTRL
Default = 0x00
Cleared by VTR
POR
NAME
CC
POR
REG INDEX
0xF3
0xF4
Watch-dog timer Configuration
Bit[0] Joy-stick Enable
=1
=0
Bit[1] Keyboard Enable
=1
=0
Bit[2] Mouse Enable
=1
=0
Bit[3] PWRLED Time-out enable
=1
=0
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = Invalid
0001 = IRQ1
0000 = Disable
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0
Bit[1] Power LED Toggle Enable, R/W
=1
=0
Bit[2] Force Timeout, W
=1
Bit[3] P20 Force Timeout Enable, R/W
= 1
= 0
Note: The P20 signal will remain high for a minimum of
1us and can remain high indefinitely. Therefore, when P20
forced timeouts are enabled, a self-clearing edge-detect
circuit is used to generate a signal which is ORed with the
WDT is reset upon an I/O read or write of the
Game Port
WDT is not affected by I/O reads or writes to
the Game Port.
WDT is reset upon a Keyboard interrupt.
WDT is not affected by Keyboard interrupts.
WDT is reset upon a Mouse interrupt
WDT is not affected by Mouse interrupts.
Enables the Power LED to toggle at a 1Hz
rate with 50 percent duty cycle while the
Watch-dog Status bit is set.
Disables the Power LED toggle during Watch-
dog timeout status.
WD timeout occurred
WD timer counting
Toggle Power LED at 1Hz rate with 50 percent
duty cycle. (1/2 sec. on, 1/2 sec. off)
Disable Power LED Toggle
Forces WD timeout event; this bit is self-clearing
Allows rising edge of P20, from the Keyboard
Controller, to force the WD timeout event. A WD
timeout event may still be forced by setting the
Force Timeout Bit, bit 2.
P20 activity does not generate the WD timeout
event.
195
DEFINITION
STATE
C
C