FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 129

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

KEYBOARD ISA INTERFACE
The FDC37B72x ISA interface is functionally
compatible with the 8042-style host interface. It
consists of the D0-7 data bus; the nIOR, nIOW
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data
Keyboard Data Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is cleared
to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output is
cleared and the OBF flag in the status register is
cleared.
AUXOBF1 must be cleared in software.
ISA ADDRESS
OUT DBB
0x60
0x64
8042 INSTRUCTION
Read.
If not enabled, the KIRQ and/or
nIOW
0
1
0
1
TABLE 57 - HOST INTERFACE FLAGS
Set OBF, and, if enabled, the KIRQ output signal goes high
TABLE 56 - ISA I/O ADDRESS MAP
nIOR
0
0
1
1
BLOCK
KDATA
KDATA
KDCTL
KDCTL
129
and the Status register, Input Data register, and
Output Data register. Table 48 shows how the
interface decodes the control signals. In addition
to the above signals, the host interface includes
keyboard
Keyboard Command Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is set to
one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
CPU-to-Host Communication
The FDC37B72x CPU can write to the Output
Data register via register DBB. A write to this
register automatically sets Bit 0 (OBF) in the
Status register. See Table 49.
Keyboard Data Write (C/D=0)
Keyboard Data Read
Keyboard Command Write (C/D=1)
Keyboard Status Read
FLAG
FUNCTION (NOTE 1)
and
mouse
IRQs.