FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 131

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

(as above). However, as the oscillator cell will
require an initialization time, either RESET must
be held active for sufficient time to allow the
oscillator to stabilize.
resume as above.
INTERRUPTS
The FDC37B72x provides the two 8042 interrupts,
the IBF and the Timer/Counter Overflow.
MEMORY CONFIGURATIONS
The FDC37B72x provides 2K of on-chip ROM and
256 bytes of on-chip RAM.
Register Definitions
Status Register
This register is cleared on a reset. This register is
read-only for the Host and read/write by the
FDC37B72x CPU.
UD
C/D
IBF
UD
D7
Writable by FDC37B72x CPU.
bits are user-definable.
(Command
whether the input data register contains
data or a command (0 = data, 1 =
command).
data/command write operation, this bit is
set to "1" if SA2 = 1 or reset to "0" if SA2
= 0.
(Input Buffer Full)- This flag is set to 1
whenever the host system writes data
into the input data register. Setting this
flag activates the FDC37B72x CPU's
nIBF (MIRQ) interrupt if enabled. When
the FDC37B72x CPU reads the input
data
automatically reset and the interrupt is
register
UD
D6
Data)-This
Program execution will
DESCRIPTION
(DBB),
During
UD
D5
TABLE 58 - STATUS REGISTER
bit
this
a
specifies
TABLE 59 - RESETS
bit
These
UD
D4
host
is
131
Host I/F Data Register
The Input Data and Output Data registers are
each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the OBF
flag and set the KIRQ output if enabled. A read of
this register will read the data from the Keyboard
Data or Command Write Buffer and clear the IBF
flag.
descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide. Table 58 shows
the
OBF
EXTERNAL CLOCK SIGNAL
The FDC37B72x Keyboard Controller clock source
is a 12 MHz clock generated from a 14.318 MHz
clock. The reset pulse must last for at least 24 16
MHz clock periods. The pulse-width requirement
applies to both internally (Vcc POR) and externally
generated reset signals. In powerdown mode, the
external clock signal is not loaded by the chip.
DEFAULT RESET CONDITIONS
The FDC37B72x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
Table 59 for the effect of each type of reset on the
internal registers.
HARDWARE RESET (RESET)
C/D
D3
contents
Refer to the KIRQ and Status register
cleared.
associated with this internal signal.
(Output Buffer Full) - This flag is set to
whenever the FDC37B72x CPU write to
the output data register (DBB). When the
host system reads the output data
register, this bit is automatically reset.
UD
D2
of
There is no output pin
the
IBF
D1
Status
OBF
D0
register.