FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 139

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

The power button has an override event as
required by the ACPI specification. If the user
presses the power button for more than four
seconds while the system is in the working state,
a hardware event is generated and the system
will transition to the off state. There are status
bits and enable bits associated with this feature
in the PM1_BLK registers.
section.
This override event utilizes power button logic to
determine that the power button (Button_In) has
been pressed for more that four seconds. The
override enable/disable bit, PWRBTNOR_EN,
allows this override function to be turned on/off.
If enabled, this override event will result in setting
the override status bit, PWRBTNOR_STS (to be
cleared by writing a 1 to its bit position - writing a
0 has no effect), clearing the regular button
status bit, PWRBTN_STS, and generating an
event to be routed into the soft power
management logic to turn off the system. The
See the ACPI
BUTTON OVERRIDE FEATURE
139
override status bit alerts the system upon power-
up that an override event was used to power
down the system, and will be used to properly
power-up the system.
Figure 11 shows the soft power management
logic with the override timer path from the button
input. The override timer counts while the button
is held (in the present implementation this would
be when the button input is high) and is cleared
upon release of the button. It has a 0.5 second
or faster resolution (run off of the 32kHz clock
divided down) and the minimum time for
triggering the override power down is four
seconds, with a maximum of 4.5 seconds. The
timer output will pulse the clear on the Flip Flop
1.
Figure 12 illustrates the timing of the blanking
period relative to Button_In and nPowerOn for
the override event.