FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 118

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

The SIRQ data frame will now support IRQ2 from
a logical device, previously IRQSER Period 3
was
Management Interrupt (nSMI).
Period 3 for IRQ2 the user should mask off the
SMI via the SMI Enable Register.
when using Period 3 for nSMI the user should
not configure any logical devices as using IRQ2.
IRQSER Period 14 is used to transfer IRQ13.
Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port
1), 5 (Ser Port 2), and 7 (KBD) shall have IRQ13
as a choice for their primary interrupt.
The SMI is enabled onto the SMI frame of the
Serial IRQ via bit 6 of SMI Enable Register 2 and
onto the SMI pin via bit 7 of the SMI Enable
Register 2.
Note: When Serial IRQs are used, nIRQ8,
nSCI and nSMI may be output on one of their
respective pin options.
Configuration Register.
Stop Cycle Control
Once all IRQ/Data Frames have completed the
Host Controller will terminate IRQSER activity by
initiating a Stop Frame. Only the Host Controller
can initiate the Stop Frame. A Stop Frame is
indicated when the IRQSER is low for two or
three clocks. If the Stop Frame’s low time is two
clocks then the next IRQSER Cycle’s sampled
mode is the Quiet mode; and any IRQSER
device may initiate a Start Frame in the second
clock or more after the rising edge of the Stop
Frame’s pulse. If the Stop Frame’s low time is
three clocks then the next IRQSER Cycle’s
sampled mode is the Continuos mode; and only
the Host Controller may initiate a Start Frame in
the second clock or more after the rising edge of
the Stop Frame’s pulse.
reserved
for
use
See the IRQ MUX
by
the
When using
Likewise,
System
118
Latency
Latency for IRQ/Data updates over the IRQSER
bus in bridge-less systems with the minimum
IRQ/Data Frames of seventeen, will range up to
96 clocks (3.84μS with a 25MHz PCI Bus or
2.88uS with a 33MHz PCI Bus). If one or more
PCI to PCI Bridge is added to a system, the
latency for IRQ/Data updates from the secondary
or tertiary buses will be a few clocks longer for
synchronous buses, and approximately double
for asynchronous buses.
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential
implementation issue related to IRQ latency. IRQ
latency could cause an EOI or ISR Read to
precede an IRQ transition that it should have
followed. This could cause a system fault. The
host interrupt controller is responsible for
ensuring that these latency issues are mitigated.
The recommended solution is to delay EOIs and
ISR Reads to the interrupt controller by the same
amount as the IRQSER Cycle latency in order to
ensure that these events do not occur out of
order.
AC/DC Specification Issue
All IRQSER agents must drive / sample IRQSER
synchronously related to the rising edge of PCI
bus clock. IRQSER (SIRQ) pin uses the
electrical specification of PCI bus.
parameters will follow PCI spec. section 4,
sustained tri-state.
Reset and Initialization
The IRQSER bus uses RESET_DRV as its reset
signal. The IRQSER pin is tri-stated by all agents
while
IRQSER Slaves are put into the (continuous)
IDLE mode. The Host Controller is responsible
for starting the initial IRQSER Cycle to collect
system’s IRQ/Data default values. The system
then follows with the Continuous/Quiet mode
protocol
subsequent
RESET_DRV
(Stop
IRQSER
Frame
is
Cycles.
active.
pulse
It
With
width)
Electrical
is
reset,
Host
for