FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 121

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

The FDC37B72x provides a set of flexible
Input/Output control functions to the system
designer through the 20 dedicated independently
programmable General Purpose I/O pins (GPIO).
Each GPIO port requires a 1-bit data register and
an 8-bit configuration control register. The data
register for each GPIO port is represented as a bit
in one of three 8-bit GPIO DATA Registers, GP1,
GP5, and GP6.
located in Logical Device Block No. 8 in the
FDC37B72x device configuration space.
GPIO
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
PIN NO.
QFP
77
78
79
80
81
82
39
91
92
83
84
85
86
87
88
89
90
4
6
2
DATA
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PCI_CLK
GPIO
nROMCS
nROMOE
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
FUNCTION
Refer to the section on Either Edge Triggered Interrupt Inputs.
At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for
These pins cannot be programmed as open drain pins in their original function.
The function of P17 or P12 is selected via the P17/P12 select bit in the Ring Filter Select
The GPIO Data and Configuration Registers are located in Logical Device Block Number 8.
alternate functions, nROMCS must stay high until those pins are finished being programmed.
Register in Logical Device 8 at 0xC6.
DEFAULT
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
Registers
All of the GPIO registers are
2
2
TABLE 50 - GENERAL PURPOSE I/O PORT ASSIGNMENTS
nSMI
nRING
WDT
LED
IRRX2
IRTX2
nMTR1
nDS1
IRQ14
DRVDEN1
IRQ11
IRQ12
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ10
FUNC. 1
are
ALT.
also
GENERAL PURPOSE I/O
-
-
-
-
-
GPIO
IRQ8
GPIO
GPIO
EETI
P17/P12
-
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
FUNC. 2
optionally
ALT.
1
DESCRIPTION
The
4
121
-
-
EETI
-
-
-
-
-
-
nSMI
EETI
EETI
nSMI
LED
nRING
WDT
P17/P12
-
-
-
FUNC. 3
ALT.
The GPIO pins can perform simple I/O or can be
individually configured to provide predefined
alternate functions.
configures all GPIO pins as non-inverting inputs.
available
FDC37B72x is in the Run state (see the Run State
GPIO Register Access section below). The GPIO
ports
configuration state register addresses are listed in
TABLE 50. Note: four bits 1, 5-7 of GP5 are not
implemented.
1
1
1
4
with
REGISTER
at
(CRFA)
(CRF6)
(CRF9)
DATA
(HEX)
GP5
GP1
GP6
their
different
5
alternate
REGISTER
VBAT Power-On-Reset
BIT NO.
addresses
DATA
0
1
2
3
4
5
6
7
0
2
3
4
0
1
2
3
4
5
6
7
functions
REGISTER
CONFIG.
when
CRCC
CRCA
CRCB
(HEX)
CRE0
CRE1
CRE2
CRE3
CRE4
CRE5
CRE6
CRE7
CRC8
CRD0
CRD1
CRD2
CRD3
CRD4
CRD5
CRD6
CRD7
and
the
5