FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 30

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller.
values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no
functionality. It can be read by bit 2 of the DSR
when in Model 30 register mode. Unaffected by
software reset.
RESET
COND.
RESET
COND.
See Table 11 for the appropriate
See Table 11 for the appropriate
N/A
N/A
7
7
N/A
N/A
6
6
N/A
N/A
5
5
N/A
30
N/A
4
4
BIT 2 - 7 RESERVED
Should be set to a logical "0"
PS/2 Model 30 Mode
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 12 shows the state of the DENSEL pin. The
DENSEL pin is set high after a hardware reset and
is unaffected by the DOR and the DSR resets.
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the
Data Register contains data bytes that give the
status of the command just executed.
N/A
N/A
3
3
NOPREC DRATE
N/A
N/A
2
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
SEL0
DRATE
SEL0
0
0
0
0