FDC37B727-NS Standard Microsystems (SMSC), FDC37B727-NS Datasheet - Page 142

• Manufacturer Part Number: FDC37B727-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B727-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Wake Events
Wake events are events that turn power on
(activate nPowerOn output) if enabled. These
events can also be enabled as SMI, SCI and
Note 1: These SCI/PME events are SMI events that are enabled through DEVINT_EN.
Note 2: These SCI events have Status and Enable bits in the PM1 registers.
Note 3: The polarity of the edge that causes the event is programmable through the polarity bit in the
The following are SMI events that are not wake events:
•
•
•
•
Any wakeup logic that affects the configuration of the wakeup events is implemented so that the
configuration of the wakeup events is retained (in the event of total power loss) upon Vtr POR.
INTERNA
SIGNALS
PINS
L
Floppy Interrupt
Parallel Port Interrupt
WDT
P12
GPIO configuration registers. The default is the low-to-high edge.
KDAT
MDAT
IRRX2
RXD2/IRRX
RXD1
nRI1
nRI2
nRING
Button
GP10-17
GP50-54, GP60-67
VTR POR
WAKE EVENTS
3
142
KDAT
MDAT
IRRX2
RXD2/IRRX
RXD1
nRI1
nRI2
nRING
Button
GPINT1
GPINT2
VTR POR
INPUT TO SOFT POWER
nPME events as shown in the following table. In
addition, these wake events set the WAK_STS
bit if enabled (see ACPI PM1_STS2 Register
description).
MANAGEMENT
SMI/SCI/PME
SMI/SCI/PME
SMI/SCI/PME
SMI/SCI/PME
SMI/SCI
SMI/SCI/PME
SMI/SCI/PME
SMI/SCI/PME
SMI/SCI
SMI/SCI
SMI/SCI
SCI
GENERATION
SMI/SCI/PME
1
2
1
1
/PME
/PME
/PME
/PME
1
1
1