XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 104

no-image

XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP7-5FFG896I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2VP7-5FFG896I
Manufacturer:
XILINX
0
Company:
Part Number:
XC2VP7-5FFG896I
Manufacturer:
XILINX
Quantity:
686
CLB Distributed RAM Switching Characteristics
Table 40: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Table 41: CLB Shift Register Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
BX/BY data inputs (DIN)
F/G address inputs
SR input
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
BX/BY data inputs (DIN)
SR input
Minimum Pulse Width, High
Minimum Pulse Width, Low
a “0” is listed, there is no positive hold time.
a “0” is listed, there is no positive hold time.
R
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
T
SRLDS
T
T
T
T
T
Symbol
WES
T
Symbol
WSS
T
T
T
SHCKO16
SHCKO32
SHCKOF5
T
T
T
T
DS
T
T
AS
T
T
T
REGXB
REGYB
REG32
REGF5
CKSH
SRPH
WPH
SRPL
WPL
REG
WC
/T
/T
/T
/T
/T
AH
DH
WEH
SRLDH
WSH
0.38/–0.07
0.70/–0.16
0.42/ 0.00
0.22/ 0.04
0.27/ 0.01
1.25
1.57
1.52
0.63
0.63
1.25
2.78
3.10
2.84
2.55
2.50
3.05
0.63
0.63
-
-7
7
Speed Grade
Speed Grade
0.77/–0.18
0.41/–0.07
0.34/ 0.01
0.47/ 0.00
0.24/ 0.05
3.12
3.49
3.18
2.88
2.83
3.42
0.72
0.72
1.38
1.75
1.68
0.72
0.72
1.44
-6
-
6
0.98/–0.21
0.47/ 0.01
0.46/–0.08
0.52/ 0.00
0.26/ 0.05
3.49
3.90
3.55
3.21
3.15
3.83
0.79
0.79
1.54
1.95
1.88
0.79
0.79
1.58
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
33

Related parts for XC2VP7-5FFG896I