XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 124

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
DS083 (v4.7) November 5, 2007
Product Specification
12/03/02
01/20/03
03/24/03
05/27/03
05/27/03
(cont’d)
Date
R
Version
(cont’d)
2.5
2.6
2.7
2.8
2.8
Updated parametric information in:
Updated parametric information in:
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Table
(single-ended) and DV
measurement.
Table
Table
Add footnote (2) to qualify Max T
Added/updated timing parameters from speedsfile v1.76.
Table
Table
Table
Table
Table
Updated time and frequency parameters as per speedsfile v1.78.
Table
Corrected I
LVCMOS18 from 20% V
Table
Jitter Calculator.
Added
Table
Table
version) due to a document compilation error. The concatenated full data sheet version
was not affected. These parameters have been restored.
Table
3.3V.
Table
Table
REFCLK2, BREFCLK, and BREFCLK2; correct T
Table
Table
Move clock parameters from
Table
Table
Table
Table
Table
XC2VP20. Added footnote specifying parameters are for Commercial Grade parts.
Table
Table
Changed V
Table
explanatory text above table.
Table 13
from XC2VP7FF672-6 to XC2VP20FF1152-6.
Table
speed grade and Production for the -5 speed grade.
Removed former Table 32, Standard Capacitive Loads.
Table
1: Correct lower limit of voltage range of V
2: Add footnote (2) regarding V
12: Add waveform diagrams
23: Indicate REFCLK upper frequency limitation; relate REFCLK parameters to
57: Add qualifying footnote to CLKOUT_DUTY_CYCLE_DLL
12: Correct DV
23: Correct T
56: Correct hyperlink in footnote (1) to point directly to Answer Record 13645.
2: Delete first table footnote and renumber all others.
3: Add "sample-tested" to I
8: Update V
10: Update LVPECL_25 DC parameters.
23: Update F
27: Update F
36: Update V
40,
61: Break out T
3: Added values for I
4: Updated/Added Typ and Max quiescent current values for XC2VP7 and
5: Added footnote specifying parameters are for Commercial Grade parts.
6: Corrected V
10: Corrected LVPECL_25 Min and Max values for V
15: Updated to show devices XC2VP7 and XC2VP20 as Preliminary for the -6
49: Updated T
56: Modified footnote referenced at CLKFX/CLKFX180 to point to the online
1: Footnote (2) rewritten to specify “one or more banks.”
54: Some DCM parameters were erroneously missing from v2.8 (single-module
Figure 6
and
Table
CCINTQ
IL
(Min) for all standards to –0.2V. Corrected V
Table 14
41: Correct parameter name "CE input (WS)" to "SR input".
and accompanying procedure for measuring standard adjustments.
OCM
www.xilinx.com
(Table
RCLK
GCLK
GTX
REF
IH
TAPTCK
IN
DCD_CLK0
PPOUT
(pin-pin and reg-reg performance): Changed device specified
(Typ) to 1.250V.
(Max) for LVTTL and LVCMOS33 standards from 3.6V to 3.45V.
Min (200 mV to 175 mV) and DV
frequency ranges. Correct T
(Typ) for HSTL Class I/II from 1.08V to 0.90V.
CCO
/T
frequency ranges. Break out T
4) and I
REF
FCLK
from 4.0 ns to 5.5 ns.
to 30% V
Table
(differential).
, I
by device type.
Typ (400 ps to 600 ps) and Max (600 ps to 1000 ps).
L
L
GJTT
, I
CCINTMIN
. Remove "Device" column, unnecessary.
(Figure 1
RPU
18,
Revision
CCAUX
parameter.
CCO
, I
Table
RPD
.
(Table
voltage droop. Renumbered other notes.
and
19,
IN
Table
Figure
RCLK
5) for XC2VP20 to 600 mA.
and V
DJ
to 0.17 UI, T
20, and
and T
GJTT
IN
2) illustrating DV
TS
IL
Max (1000 mV to 2000 mV).
IH
from –0.5V to –0.3V for
(Max) for LVCMOS15 and
by operating speed.
FCLK
and V
Table 21
values and unit of
.
RJ
IL
. Added
to o.18 UI.
to
OUT
Table
Module 3 of 4
16.
53

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