XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 21

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Functional Description: RocketIO Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO MGT, including digital and analog design consid-
erations, refer to the
RocketIO Overview
Up to twenty RocketIO MGTs are available. The MGT is
designed to operate at any baud rate in the range of
622 Mb/s to 3.125 Gb/s per channel. This includes specific
baud rates used by various standards as listed in
The RocketIO MGT consists of the Physical Media Attach-
ment (PMA) and Physical Coding Sublayer (PCS). The
PMA contains the 3.125 Gb/s serializer/deserializer (SER-
DES), TX/RX buffers, clock generator, and clock recovery
circuitry. The PCS contains the bypassable 8B/10B
encoder/ decoder, elastic buffers, and Cyclic Redundancy
Check (CRC) units. The encoder and decoder handle the
8B/10B coding scheme. The elastic buffers support the
clock correction (rate matching) and channel bonding fea-
tures. The CRC units perform CRC generation and check-
ing.
See
between the RocketIO X PMA/PCS and the RocketIO
PMA/PCS.
PMA
Transmitter Output
The RocketIO transceiver is implemented in Current Mode
Logic (CML). A CML transmitter output consists of transis-
tors configured as shown in
supply and offers easy interface requirements. In this con-
figuration, both legs of the driver, VP and VN, sink current,
with one leg always sinking more current than its comple-
ment. The CML output consists of a differential pair with
50Ω (or, optionally, 75Ω) source resistors. The signal swing
is created by switching the current in a common-source dif-
ferential pair.
DS083 (v4.7) November 5, 2007
Product Specification
Table 7, page
Figure 8: CML Output Configuration
R
17, for a summary of the differences
RocketIO Transceiver User
CML Output Driver
Figure
V
V
P
N
V
8. CML uses a positive
P
-
V
N
DS083-2_66_052104
=
V
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DATA
Table
Guide.
www.xilinx.com
4.
Figure 10, page 11
RocketIO transceiver and its FPGA interface signals.
Table 4: Protocols Supported by RocketIO Transceiver
Transmitter Termination
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. The output driver and
termination are powered by V
CML approach with selectable 50Ω or 75Ω termination to
TXP and TXN as shown in
Notes:
1.
2.
Fibre Channel
Gigabit Ethernet
10Gbit Ethernet
Infiniband
Aurora
Custom Protocol
One channel is considered to be one transceiver.
Virtex-II Pro MGT can support the 10G Fibre Channel data rates of
3.1875 Gb/s across 6" of standard FR-4 PCB and one connector
(Molex 74441 or equivalent) with a bit error rate of 10
Figure 9: RocketIO Transmit Termination
Mode
50/75Ω
shows a high-level block diagram of the
Figure
1, 2, 3, 4, ...
1, 2, 3, 4, ...
TTX
Channels
(Lanes)
1, 4, 12
. This configuration uses a
50/75Ω
1
1
4
9.
(1)
0.622 – 3.125
I/O Bit Rate
VTTX
TXP
TXN
up to 3.125
3.1875
-12
ug083_33_061504
Module 2 of 4
(Gb/s)
3.125
1.06
2.12
1.25
or better.
2.5
(2)
10

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