XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 99

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued)
DS083 (v4.7) November 5, 2007
Product Specification
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL, Class III, with DCI
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
HSTL_IV_DCI_18
HSTL_III_DCI_18
HSTL_II_DCI_18
IOSTANDARD
HSTL_I_DCI_18
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
SSTL18_II_DCI
SSTL18_I_DCI
HSTL_IV_DCI
SSTL2_II_DCI
HSTL_III_DCI
SSTL2_I_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_II_DCI
HSTL_III_18
HSTL_IV_18
HSTL_I_DCI
HSTL_II_18
HSTL_I_18
GTLP_DCI
SSTL18_II
Attribute
SSTL18_I
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
SSTL2_II
GTL_DCI
HSTL_IV
HSTL_III
SSTL2_I
HSTL_II
T
T
T
T
T
T
T
T
T
OHSTL_III_DCI_18
OHSTL_IV_DCI_18
T
T
T
OHSTL_II_DCI_18
T
T
T
T
T
T
T
OHSTL_I_DCI_18
T
T
OSSTL18_II_DCI
T
OLVDCI_DV2_25
OLVDCI_DV2_18
OLVDCI_DV2_15
Parameter
OSSTL18_I_DCI
T
OSSTL2_II_DCI
T
OHSTL_III_DCI
OHSTL_IV_DCI
T
OSSTL2_I_DCI
OHSTL_IIII_18
T
T
T
T
T
OHSLVDCI_15
OHSLVDCI_18
OHSLVDCI_25
OHSLVDCI_33
OHSTL_II_DCI
OHSTL_IV_18
OHSTL_I_DCI
T
T
T
T
OHSTL_II_18
T
T
OHSTL_I_18
OGTLP_DCI
OSSTL18_II
Timing
OSSTL18_I
OLVDCI_33
OLVDCI_25
OLVDCI_18
OLVDCI_15
OHSTL_IIII
OGTL_DCI
OHSTL_IV
OSSTL2_II
OSSTL2_I
OHSTL_II
0.30
0.31
0.15
0.56
0.30
0.36
0.19
0.80
0.45
0.63
0.22
0.72
0.56
0.65
1.00
0.06
0.30
0.60
1.00
0.65
0.56
0.72
1.21
0.05
0.55
0.47
0.31
1.81
0.55
0.24
0.35
1.48
0.54
0.24
0.48
0.48
-7
Speed Grade
0.35
0.35
0.17
0.64
0.35
0.41
0.22
0.92
0.51
0.72
0.25
0.83
0.64
0.75
1.15
0.07
0.34
0.69
1.15
0.75
0.64
0.83
1.39
0.06
0.63
0.54
0.36
2.08
0.63
0.28
0.40
1.70
0.62
0.28
0.56
0.56
-6
0.38
0.39
0.19
0.70
0.38
0.45
0.24
1.01
0.56
0.79
0.27
0.91
0.71
0.82
1.26
0.08
0.38
0.76
1.26
0.82
0.71
0.91
1.53
0.07
0.69
0.60
0.40
2.29
0.70
0.31
0.44
1.87
0.68
0.31
0.61
0.61
-5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28

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