XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 42

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II Pro XCITE DCI provides controlled impedance
drivers and on-chip termination for single-ended and differ-
ential I/Os. This eliminates the need for external resistors
and improves signal integrity. The DCI feature can be used
on any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in
When used with a terminated I/O standard, the value of the
resistors are specified by the standard (typically 50Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (20Ω to 100Ω). For all series and parallel termina-
tions listed in
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
DS083 (v4.7) November 5, 2007
Product Specification
Figure 26: DCI in a Virtex-II Pro Bank
R
Figure
Table 13
1 Bank
DCI
DCI
DCI
DCI
26.
and
VRN
VRP
Table
V CCO
14, the reference resistors
GND
DS031_50_101200
R
R
REF
REF
(1%)
(1%)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
www.xilinx.com
Controlled Impedance Drivers (Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z
input buffers also support LVDCI and LVDCI_DV2.
Table 13: SelectIO-Ultra Controlled Impedance Buffers
Controlled Impedance Terminations (Parallel)
DCI also provides on-chip termination for SSTL2, SSTL18,
HSTL (Class I, II, III, or IV), LVDS_25, LVDSEXT_25, and
GTL/GTLP receivers or transmitters on bidirectional lines.
Table 14
available in Virtex-II Pro devices. V
ing to
and GTLP_DCI, due to the on-chip termination resistor.
Table 14: SelectIO-Ultra Buffers With On-Chip Parallel
Termination
Notes:
1.
SSTL Class I, 2.5V
SSTL Class II, 2.5V
SSTL Class I, 1.8V
SSTL Class II, 1.8V
HSTL Class I
HSTL Class I, 1.8V
HSTL Class II
HSTL Class II, 1.8V
HSTL Class III
HSTL Class III, 1.8V
HSTL Class IV
HSTL Class IV, 1.8V
GTL
GTL Plus
Virtex-II Pro DCI
SSTL compatible.
I/O Standard
V
3.3V
2.5V
1.8V
1.5V
Description
CCO
Table
Z
Figure 27: Internal Series Termination
and
10. There is a V
IOB
Table 15
V
CCO
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
= 3.3V, 2.5 V, 1.8 V, or 1.5 V
DCI
list the on-chip parallel terminations
Termination
HSTL_IV_18
HSTL_III_18
HSTL_II_18
HSTL_I_18
SSTL18_II
SSTL18_I
SSTL2_II
HSTL_IV
External
SSTL2_I
HSTL_III
HSTL_II
HSTL_I
GTLP
GTL
CCO
IOSTANDARD Attribute
Z
0
requirement for GTL_DCI
CCO
DCI Half Impedance
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
must be set accord-
HSTL_III_DCI_18
HSTL_IV_DCI_18
HSTL_II_DCI_18
SSTL2_II_DCI
HSTL_I_DCI_18
SSTL2_I_DCI
SSTL18_II_DCI
SSTL18_I_DCI
HSTL_IV_DCI
HSTL_III_DCI
HSTL_II_DCI
Termination
HSTL_I_DCI
N/A
0
GTLP_DCI
GTL_DCI
). Virtex-II Pro
On-Chip
DS083-2_09_082902
Module 2 of 4
(1)
(1)
31

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