XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 25

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Receiver Buffer
The receiver includes buffers (FIFOs) in the datapath. This
section gives the reasons for including the buffers and out-
lines their operation.
The receiver buffer is required for two reasons:
The receiver uses an elastic buffer, where "elastic" refers to
the ability to modify the read pointer for clock correction and
channel bonding.
Comma Detection
Word alignment is dependent on the state of comma detect
bits. If comma detect is enabled, the transceiver recognizes
up to two 10-bit preprogrammed characters. Upon detection
of the character or characters, the comma detect output is
driven high and the data is synchronously aligned. If a
comma is detected and the data is aligned, no further align-
ment alteration takes place. If a comma is received and
realignment is necessary, the data is realigned and an indi-
cation is given at the receiver interface. The realignment
indicator is a distinct output.
The transceiver continuously monitors the data for the pres-
ence of the 10-bit character(s). Upon each occurrence of a
10-bit character, the data is checked for word alignment. If
comma detect is disabled, the data is not aligned to any par-
ticular pattern. The programmable option allows a user to
align data on comma+, comma–, both, or a unique
user-defined and programmed sequence.
Clock Correction
RXRECCLK (the recovered clock) reflects the data rate of
the incoming data. RXUSRCLK defines the rate at which
the FPGA fabric consumes the data. Ideally, these rates are
identical. However, since the clocks typically have different
sources, one of the clocks will be faster than the other. The
receiver buffer accommodates this difference between the
clock rates. See
Nominally, the buffer is always half full. This is shown in the
top buffer,
buffered data not yet read. Received data is inserted via the
write pointer under control of RXRECCLK. The FPGA fabric
reads data via the read pointer under control of RXUSR-
CLK. The half full/half empty condition of the buffer gives a
cushion for the differing clock rates. This operation contin-
ues indefinitely, regardless of whether or not "meaningful"
data is being received. When there is no meaningful data to
be received, the incoming data will consist of IDLE charac-
ters or other padding.
If RXUSRCLK is faster than RXRECCLK, the buffer
becomes more empty over time. The clock correction logic
DS083 (v4.7) November 5, 2007
Product Specification
Clock correction to accommodate the slight difference
in frequency between the recovered clock RXRECCLK
and the internal FPGA user clock RXUSRCLK
Channel bonding to allow realignment of the input
stream to ensure proper alignment of data being read
through multiple transceivers
Figure
R
Figure
12, where the shaded area represents
12.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
www.xilinx.com
corrects for this by decrementing the read pointer to reread
a repeatable byte sequence. This is shown in the middle
buffer,
to the value represented by the dashed pointer.
Removable sequence
By decrementing the read pointer instead of incrementing it in
the usual fashion, the buffer is partially refilled. The transceiver
design will repeat a single repeatable byte sequence when
necessary to refill a buffer. If the byte sequence length is
greater than one, and if attribute CLK_COR_REPEAT_WAIT
is 0, then the transceiver may repeat the same sequence mul-
tiple times until the buffer is refilled to the desired extent.
Similarly, if RXUSRCLK is slower than RXRECCLK, the
buffer will fill up over time. The clock correction logic cor-
rects for this by incrementing the read pointer to skip over a
removable byte sequence that need not appear in the final
FPGA fabric byte stream. This is shown in the bottom buffer,
Figure
value represented by the dashed pointer. This accelerates
the emptying of the buffer, preventing its overflow. The
transceiver design will skip a single byte sequence when
necessary to partially empty a buffer. If attribute
CLK_COR_REPEAT_WAIT is 0, the transceiver may also
skip two consecutive removable byte sequences in one step
to further empty the buffer when necessary.
These operations require the clock correction logic to recog-
nize a byte sequence that can be freely repeated or omitted
in the incoming data stream. This sequence is generally an
IDLE sequence, or other sequence comprised of special
values that occur in the gaps separating packets of mean-
ingful data. These gaps are required to occur sufficiently
often to facilitate the timely execution of clock correction.
Channel Bonding
Some gigabit I/O standards such as Infiniband specify the
use of multiple transceivers in parallel for even higher data
rates. Words of data are split into bytes, with each byte sent
over a separate channel (transceiver). See
Read
Figure
12, where the solid read pointer increments to the
Figure 12: Clock Correction in Receiver
RXUSRCLK
Read
12, where the solid read pointer decrements
Repeatable sequence
Read
Buffer less than half -full (emptying)
Buffer more than half-full (filling up)
"Nominal" condition: buffer half-full
Write
RXRECCLK
Write
Figure
Write
Module 2 of 4
DS083-2_15_100901
13.
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