XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 18



Manufacturer Part Number
Xilinx Inc
Virtex™-II Pror

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
cation is given at the receiver interface. The realignment
indicator is a distinct output.
The transceiver continuously monitors the data for the pres-
ence of the 10-bit character(s). Upon each occurrence of a
10-bit character, the data is checked for word alignment. If
comma detect is disabled, the data is not aligned to any par-
ticular pattern. The programmable option allows a user to
align data on comma+, comma–, both, or a unique
user-defined and programmed sequence.
Comma detection has been expanded beyond 10-bit sym-
bol detection and alignment to include 8-bit symbol detec-
tion and alignment for 16-, 20-, 32-, and 40-bit paths. The
ability to detect symbols, and then either align to 1-word,
2-word, or 4-word boundaries is included. The RXSLIDE
input allows the user to “slide” or “slip” the alignment by one
bit in each 16-, 20-, 32- and 40-bit mode at any time for
SONET applications. Comma detection can be bypassed
when needed.
Clock Correction
RXRECCLK (the recovered clock) reflects the data rate of
the incoming data. RXUSRCLK defines the rate at which
the FPGA fabric consumes the data. Ideally, these rates are
identical. However, since the clocks typically have different
sources, one of the clocks will be faster than the other. The
receiver buffer accommodates this difference between the
clock rates. See
Removable sequence
Nominally, the buffer is always half full. This is shown in the
top buffer,
ered data not yet read. Received data is inserted via the
write pointer under control of RXRECCLK. The FPGA fabric
reads data via the read pointer under control of RXUSR-
CLK. The half full/half empty condition of the buffer gives a
cushion for the differing clock rates. This operation contin-
ues indefinitely, regardless of whether or not "meaningful"
data is being received. When there is no meaningful data to
be received, the incoming data will consist of IDLE charac-
ters or other padding.
DS083 (v4.7) November 5, 2007
Product Specification
Figure 6: Clock Correction in Receiver
Repeatable sequence
6, where the shaded area represents buff-
Buffer less than half -full (emptying)
Buffer more than half-full (filling up)
"Nominal" condition: buffer half-full
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
If RXUSRCLK is faster than RXRECCLK, the buffer
becomes more empty over time. The clock correction logic
corrects for this by decrementing the read pointer to reread
a repeatable byte sequence. This is shown in the middle
the value represented by the dashed pointer. By decrement-
ing the read pointer instead of incrementing it in the usual
fashion, the buffer is partially refilled. The transceiver design
will repeat a single repeatable byte sequence when neces-
sary to refill a buffer. If the byte sequence length is greater
than one, and if attribute CLK_COR_REPEAT_WAIT is 0,
then the transceiver may repeat the same sequence multi-
ple times until the buffer is refilled to the desired extent.
Similarly, if RXUSRCLK is slower than RXRECCLK, the
buffer will fill up over time. The clock correction logic cor-
rects for this by incrementing the read pointer to skip over a
removable byte sequence that need not appear in the final
FPGA fabric byte stream. This is shown in the bottom buffer,
value represented by the dashed pointer. This accelerates
the emptying of the buffer, preventing its overflow. The
transceiver design will skip a single byte sequence when
necessary to partially empty a buffer. If attribute
CLK_COR_REPEAT_WAIT is 0, the transceiver may also
skip two consecutive removable byte sequences in one step
to further empty the buffer when necessary.
These operations require the clock correction logic to recog-
nize a byte sequence that can be freely repeated or omitted
in the incoming data stream. This sequence is generally an
IDLE sequence, or other sequence comprised of special
values that occur in the gaps separating packets of mean-
ingful data. These gaps are required to occur sufficiently
often to facilitate the timely execution of clock correction.
Channel Bonding
Some gigabit I/O standards such as Infiniband specify the
use of multiple transceivers in parallel for even higher data
rates. Words of data are split into bytes, with each byte sent
over a separate channel (transceiver). See
The top half of the figure shows the transmission of words
split across four transceivers (channels or lanes). PPPP,
QQQQ, RRRR, SSSS, and TTTT represent words sent over
the four channels.
The bottom-left portion of
in the FPGA’s receivers at the other end of the four chan-
nels. Due to variations in transmission delay—especially if
the channels are routed through repeaters—the FPGA fab-
ric might not correctly assemble the bytes into complete
words. The bottom-left illustration shows the incorrect
assembly of data words PQPP, QRQQ, RSRR, and so forth.
To support correction of this misalignment, the data stream
includes special byte sequences that define corresponding
points in the several channels. In the bottom half of
characters. Each receiver recognizes the "P" channel bond-
6, where the solid read pointer increments to the
7, the shaded "P" bytes represent these special
6, where the solid read pointer decrements to
Figure 7
shows the initial situation
Module 2 of 4

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