XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 16
Manufacturer Part Number
IC FPGA VIRTEX-II PRO 896-FBGA
Specifications of XC2VP7-5FFG896I
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
RXP and RXN as shown in
termination styles, including high-side, low-side, and differ-
ential (floating or active). This configuration supports
receiver termination compatible to Virtex-II Pro devices,
Fabric Data Interface
Internally, the PCS operates in either 2-byte mode (16/20
bits) or 4-byte mode (32/40 bits). When in 2-byte mode, the
FPGA fabric interface can either be 1, 2, or 4 bytes wide.
When in 4-byte mode, the FPGA fabric interface can either
be 4 or 8 bytes wide. When accompanied by the predefined
modes of the PMA, the user thus has a large combination of
protocols and data rates from which to choose.
USRCLK2 clocks data on the fabric side, while USRCLK
clocks data on the PCS side. This creates distinct USR-
CLK/USRCLK2 frequency ratios for different combinations
of fabric and internal data widths.
USRCLK2-to-USRCLK ratios for the different possible com-
binations of data widths.
Table 2: Clock Ratios for Various Data Widths
As a general guide, use 2-byte internal data width mode
when the serial speed is below 5 Gb/s, and 4-byte internal
data width mode when the serial speed is greater than
5 Gb/s. In 2-byte mode, the PCS processes 4-byte data
every other byte.
DS083 (v4.7) November 5, 2007
Each edge of slower clock must align with falling edge of faster clock.
Frequency Ratio of USRCLK:USRCLK2
5. This supports multiple
Figure 5: RocketIO X Receive Termination
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
using a CML (high-side) termination to an active supply of
1.8V – 2.5V. For DC coupling of two Virtex-II Pro X devices,
a 1.5V CML termination for VTRX is recommended.
No fixed phase relationship is assumed between REFCLK,
RXRECCLK, and/or any other clock that is not tied to either
of these clocks. When RXUSRCLK and RXUSRCLK2 have
different frequencies, each edge of the slower clock is
aligned to a falling edge of the faster clock. The same rela-
tionships apply to TXUSRCLK and TXUSRCLK2.
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of
data to the transmitter. Each character can be either 8 bits
or 10 bits wide. If 8-bit data is applied, the additional inputs
become control signals for the 8B/10B encoder. When the
8B/10B encoder is bypassed, the 10-bit character order is
generated as follows:
The RocketIO X PCS features a 64B/66B encoder/decoder,
scrambler/descrambler, and gearbox functions that can be
bypassed as needed. The encoder is compliant with IEEE
The bypassable scrambler operates on the read side of the
transmit FIFO. The scrambler uses the following generator
polynomial to scramble 64B/66B payload data:
The scrambler works in conjunction with the gearbox, which
frames 64B/66B data for the PMA. The gearbox should
always be enabled when using the 64B/66B protocal.
G(x) = 1 + x
(last bit transmitted is TXDATA)
(first bit transmitted)
Module 2 of 4