XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 61

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Figure 57
In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight
down). To reduce power consumption, any unused clock branches remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in
The Virtex-II Pro global clock buffer BUFG can also be con-
figured as a clock enable/disable circuit
as a two-input clock multiplexer
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE and S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.
DS083 (v4.7) November 5, 2007
Product Specification
Figure 58: Virtex-II Pro BUFG Function
Figure
shows clock distribution in Virtex-II Pro devices.
R
58.
I
BUFG
NW
SW
DS031_61_101200
8 BUFGMUX
(Figure
16 Clocks
8 BUFGMUX
O
Figure 57: Virtex-II Pro Clock Distribution
(Figure
60). A functional
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
59), as well
NE
SE
www.xilinx.com
NW
SW
BUFGCE
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
BUFGMUX
BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the I
a High on S selects the I
the other is done in such a way that the output High and Low
time is never shorter than the shortest High or Low time of
either input clock. As long as the presently selected clock is
High, any level change of S has no effect.
8
8
8 BUFGMUX
8 BUFGMUX
Figure 59: Virtex-II Pro BUFGCE Function
16 Clocks
CE
I
8
8
BUFGCE
1
input. Switching from one clock to
DS083-2_45_122001
DS031_62_101200
O
8 max
SE
NE
Module 2 of 4
0
input,
50

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