XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 27
Manufacturer Part Number
IC FPGA VIRTEX-II PRO 896-FBGA
Specifications of XC2VP7-5FFG896I
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
CRC may adjust certain trailing bytes to generate the
required running disparity at the end of the packet.
On the receiver side, the CRC logic verifies the received
CRC value, supporting the same standards as above.
The CRC logic also supports a user mode, with a simple
user-defined SOP and EOP characters.
In order to facilitate testing without having the need to either
apply patterns or measure data at GHz rates, two program-
mable loop-back features are available.
One option, serial loopback, places the gigabit transceiver
into a state where transmit data is directly fed back to the
receiver. An important point to note is that the feedback path
is at the output pads of the transmitter. This tests the
entirety of the transmitter and receiver.
The second option, parallel loopback, checks the digital cir-
cuitry. When parallel loopback is enabled, the serial loop-
back path is disabled. However, the transmitter outputs
DS083 (v4.7) November 5, 2007
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
remain active, and data can be transmitted. If TXINHIBIT is
asserted, TXP is forced to 0 until TXINHIBIT is de-asserted.
The receiver and transmitter have their own synchronous
reset inputs. The transmitter reset recenters the transmis-
sion FIFO, and resets all transmitter registers and the
8B/10B decoder. The receiver reset recenters the receiver
elastic buffer, and resets all receiver registers and the
8B/10B encoder. Neither reset has any effect on the PLLs.
All RocketIO transceivers in the FPGA, whether instantiated
in the design or not, must be connected to power and
ground. Unused transceivers can be powered by any 2.5V
source, and passive filtering is not required.
The Power Down module is controlled by the transceiver’s
POWERDOWN input pin. The Power Down pin on the
FPGA package has no effect on the transceiver.
Module 2 of 4