XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 133

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Table 4: Virtex-II Pro Pin Definitions (Continued)
DS083 (v4.7) November 5, 2007
Product Specification
Dedicated Pins:
Other Pins:
CCLK
PROG_B
DONE
M2, M1, M0
HSWAP_EN
TCK
TDI
TDO
TMS
PWRDWN_B
DXN, DXP
V
RSVD
V
V
V
GND
AVCCAUXRX#
AVCCAUXTX#
BATT
CCO
CCAUX
CCINT
GCLKx (S/P)
VRP
VRN
V
Pin Name
REF
R
(1)
(unsupported)
Input/Output
Input/Output
Input/Output
(open-drain)
Direction
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
N/A
These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
These pins can be used to clock the RocketIO transceiver. See the
Transceiver User Guide
This pin is for the DCI voltage reference resistor of P transistor (per bank).
This pin is for the DCI voltage reference resistor of N transistor (per bank).
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
Configuration clock. Output in Master mode or Input in Slave mode.
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
Configuration mode selection. Pin is biased by V
should not connect to 3.3V unless 100Ω series resistors are used. The mode pins are
not to be toggled (changed) while in operation during and after configuration.
Enable I/O pull-ups during configuration.
Boundary Scan Clock. This pin is 3.3V compatible.
Boundary Scan Data Input. This pin is 3.3V compatible.
Boundary Scan Data Output. Pin is open-drain and can be pulled up to 3.3V. It is
recommended that the external pull-up be greater than 200Ω. There is no internal
pull-up.
Boundary Scan Mode Select. This pin is 3.3V compatible.
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Connect to V
used.)
Reserved pin - do not connect.
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Analog power supply for receive circuitry of the RocketIO MGT (2.5V).
Analog power supply for transmit circuitry of the RocketIO MGT (2.5V).
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
www.xilinx.com
for design guidelines and BREFCLK-specific pins, by device.
Description
CCAUX
CCAUX
(must be 2.5V). These pins
or GND if battery not
RocketIO
Module 4 of 4
5

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