XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 429

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Revision History
This section records the change history for this module of the data sheet.
DS083 (v4.7) November 5, 2007
Product Specification
01/31/02
08/14/02
08/27/02
09/27/02
11/20/02
12/03/02
01/20/03
05/19/03
06/19/03
08/25/03
12/10/03
02/19/04
03/09/04
06/30/04
Date
R
Version
2.5.1
2.5.3
2.5.5
3.1.1
1.0
2.0
2.1
2.2
2.3
2.4
2.5
3.0
3.1
4.0
Initial Xilinx release.
Added package and pinout information for new devices.
Corrected
692 to 644.
Added Number of Differential Pairs data to
Corrections in
Added and removed package/pinout information for existing devices:
Merged in DS110-4 (Module 4 of Virtex-II Pro X data sheet). Added data on available
Pb-free packages and updated package diagrams for affected devices.
Updated SelectIO-Ultra information in
Reclassified GCLKx (S/P) pins as Input/Output, since these pins can be used as
normal I/Os if not used as clocks.
Added cautionary note to PWRDWN_B pin, indicating that this function is not
supported.
In
Added section
Added notation of "open-drain" to TDO pin in
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
Recompiled for backward compatibility with Acrobat 4 and above. No content
Corrected direction for RXNPAD and TXPPAD in
In
In
Added FG676 package pinouts
Added package diagram
Added clarification to
nature of pins D0/DIN and BUSY/DOUT during configuration.
The final GND pin in each of six pinout tables was inadvertently deleted in v2.5.1. This
revision restores the deleted GND pins as follows:
-
-
-
-
-
-
Table
Table
-5 and -6, are released to Production status.
Table
-
-
-
changes.
Table
Table
Table
Pin A1,
Pin AF26,
Pin AN34,
Pin E1,
Pin C38,
Pin E1,
For signals TDI, TMS, and TCK, added: Pins are 3.3V-compatible.
For signals M2, M1, M0, added: Tie to 3.3V only with 100Ω series resistor.
No toggling during or after configuration.
For signal TDO, added: No internal pull-up. External pull-up to 3.3V OK with
resistor greater than 200Ω.
4: Deleted Note 2, obsolete. There is only one GNDA pin per MGT.
4: Deleted pins ALT_VRP and ALT_VRN. Not used in Virtex-II Pro FPGAs.
4, signal descriptions column:
Table 2
1, added FG676 package information.
3, added FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
12, removed FF1517 package option for XC2VP40.
Table
Table 6, page 16
Table 11, page 130
Table 14, page 253
Table 12, page 162
and
Table 7, page 30
BREFCLK Pin Definitions, page
Table 10, page 98
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
4:
www.xilinx.com
Table 3
Table 4
(Figure
entries for XC2VP30, FF1152 package, maximum I/Os from
(FG456)
and all device pinout tables regarding the dual-use
(Table
(FF1148)
(FF1696)
(FG676)
3) for FG676 package.
(FF1517)
(FF1152)
Revision
Table
7) for XC2VP20, XC2VP30, and XC2VP40.
Table
4. (Table deleted in v2.3.)
3. Removed former Table 4.
Table
Table 4
5.
4.
(formerly Table 5).
Module 4 of 4
301

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