XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 26

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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The top half of the figure shows the transmission of words
split across four transceivers (channels or lanes). PPPP,
QQQQ, RRRR, SSSS, and TTTT represent words sent over
the four channels.
The bottom-left portion of
tion in the FPGA’s receivers at the other end of the four
channels. Due to variations in transmission delay—espe-
cially if the channels are routed through repeaters—the
FPGA fabric might not correctly assemble the bytes into
complete words. The bottom-left illustration shows the
incorrect assembly of data words PQPP, QRQQ, RSRR,
and so forth.
To support correction of this misalignment, the data stream
includes special byte sequences that define corresponding
points in the several channels. In the bottom half of
Figure
characters. Each receiver recognizes the "P" channel bond-
ing character, and remembers its location in the buffer. At
some point, one transceiver designated as the master
instructs all the transceivers to align to the channel bonding
character "P" (or to some location relative to the channel
bonding character).
After this operation, words transmitted to the FPGA fabric
are properly aligned: RRRR, SSSS, TTTT, and so forth, as
shown in the bottom-right portion of
that the channels remain properly aligned following the
channel bonding operation, the master transceiver must
also control the clock correction operations described in the
previous section for all channel-bonded transceivers.
DS083 (v4.7) November 5, 2007
Product Specification
Full word SSSS sent over four channels, one byte per channel
Before channel bonding
13, the shaded "P" bytes represent these special
Figure 13: Channel Bonding (Alignment)
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
RXUSRCLK
R
Read
In Transmitters:
In Receivers:
Figure 13
Channel (lane) 0
Channel (lane) 1
Channel (lane) 2
Channel (lane) 3
shows the initial situa-
After channel bonding
Figure
P Q R S T
RXUSRCLK
P Q R S T
P Q R S T
P Q R S T
Read
13. To ensure
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DS083-2_16_010202
www.xilinx.com
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is fre-
quency-locked to its read pointer (REFCLK). Therefore,
clock correction and channel bonding are not required. The
purpose of the transmitter's buffer is to accommodate a
phase difference between TXUSRCLK and REFCLK. A
simple FIFO suffices for this purpose. A FIFO depth of four
will permit reliable operation with simple detection of over-
flow or underflow, which could occur if the clocks are not fre-
quency-locked.
RocketIO Configuration
This section outlines functions that can be selected or con-
trolled by configuration. Xilinx implementation software sup-
ports 16 transceiver primitives, as shown in
Each of the primitives in
the configuration attributes, allowing some number of them
to be modified by the user. Refer to the
ceiver User Guide
Table 6: Supported RocketIO MGT Protocol Primitives
Other RocketIO Features and Notes
CRC
The RocketIO transceiver CRC logic supports the 32-bit
invariant CRC calculation used by Infiniband, FibreChannel,
and Gigabit Ethernet.
On the transmitter side, the CRC logic recognizes where the
CRC bytes should be inserted and replaces four place-
holder bytes at the tail of a data packet with the computed
CRC. For Gigabit Ethernet and FibreChannel, transmitter
Notes:
1. For more information on the Aurora protocol, visit
GT_CUSTOM
GT_FIBRE_CHAN_1
GT_FIBRE_CHAN_2
GT_FIBRE_CHAN_4
GT_ETHERNET_1
GT_ETHERNET_2
GT_ETHERNET_4
GT_XAUI_1
GT_XAUI_2
GT_XAUI_4
GT_INFINIBAND_1
GT_INFINIBAND_2
GT_INFINIBAND_4
GT_AURORA_1
GT_AURORA_2
GT_AURORA_4
http://www.xilinx.com
(1)
(1)
(1)
for more details.
Fully customizable by user
Fibre Channel, 1-byte data path
Fibre Channel, 2-byte data path
Fibre Channel, 4-byte data path
Gigabit Ethernet, 1-byte data path
Gigabit Ethernet, 2-byte data path
Gigabit Ethernet, 4-byte data path
10-gigabit Ethernet, 1-byte data path
10-gigabit Ethernet, 2-byte data path
10-gigabit Ethernet, 4-byte data path
Infiniband, 1-byte data path
Infiniband, 2-byte data path
Infiniband, 4-byte data path
1-byte data path
2-byte data path
4-byte data path
Table 6
.
defines default values for
RocketIO Trans-
Table
Module 2 of 4
6.
15

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