XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 69

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as DCI.
Readback
In this mode, configuration data from the Virtex-II Pro FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary-Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM+, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Pro Platform FPGA User Guide.
Bitstream Encryption
Virtex-II Pro devices have an on-chip decryptor using one or
two sets of three keys for triple-key Data Encryption Stan-
dard (DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
device is not powered. Virtex-II Pro devices can be config-
Revision History
This section records the change history for this module of the data sheet.
DS083 (v4.7) November 5, 2007
Product Specification
01/31/02
06/13/02
09/03/02
09/27/02
11/20/02
12/03/02
01/20/03
Date
R
Version
1.0
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release.
New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
Revised
Updated
use of I/O standards.
In section
In section
implementation of 3.3V I/O standards.
Table
Table
Table
Added mention of LVTTL and PCI with respect to SelectIO-Ultra configurations. See
section
Added qualification to features vs. Virtex-II (open-drain output pin TDO does not have
internal pull-up resistor)
Table 7: Added HSTL18 (I, II, III, & IV) and HSTL18_DCI (I,II, III & IV) to 1.8V VCCO
row. [Table deleted in v2.6.]
Added
v2.6.]
Table 8: Numerous revisions. [Table deleted in v2.6.]
BATT
8: Added rows for LVTTL, LVCMOS33, and PCI-X.
8: Added LVTTL and LVCMOS33 to compatible 3.3V cells. [Table deleted in
33: Correct bitstream lengths.
Figure
Input/Output Individual Options
Reset
Table
RocketIO
Input/Output Blocks
pin, when the
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
28,
8, which lists compatible input standards. [Table deleted in v2.6.]
and
Figure
www.xilinx.com
Power
Overview, corrected max number of MGTs from 16 to 24.
29, and
sections.
ured with the corresponding encrypted bitstream, using any
of the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the
Your local FAE can also provide specific information on this
feature.
Partial Reconfiguration
Partial reconfiguration of Virtex-II Pro devices can be
accomplished in either Slave SelectMAP mode or Bound-
ary-Scan mode. Instead of resetting the chip and doing a
full configuration, new data is loaded into a specified area of
the chip, while the rest of the chip remains in operation.
Data is loaded on a column basis, with the smallest load unit
being a configuration “frame” of the bitstream (device size
dependent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
For more information on Partial Reconfiguration in
Virtex-II Pro devices, please refer to Xilinx Application Note
XAPP290
(IOBs), added references to XAPP653 regarding
Figure
Revision
, Two Flows for Partial Reconfiguration.
and
30, which provide examples illustrating the
Figure
Virtex-II Pro Platform FPGA User Guide
22.
Module 2 of 4
58
.

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