XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 110

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Master/Slave SelectMAP Parameters
Figure 10
Virtex-II Pro Platform FPGA User Guide
Table 48: SelectMAP Mode Write Timing Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
CCLK
is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
R
DATA[0:7] setup/hold
CS_B setup/hold
RDWR_B setup/hold
BUSY propagation delay
Maximum start-up frequency
Maximum frequency
Maximum frequency with no handshake
RDWR_B
DATA[0:7]
BUSY
CCLK
CS_B
Description
Figure 10: SelectMAP Mode Data Loading Sequence (Generic)
T
T
SMCCW
SMCSCC
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
5
T
3
SMDCC
1
No Write
.
7
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
T
SMCKBY
www.xilinx.com
Write
References
2
Figure
1/2
3/4
5/6
7
T
SMCCD
No Write
T
T
T
SMCSCC
F
SMCCW
SMDCC
CC_SELECTMAP
F
CC_STARTUP
T
Symbol
F
SMCKBY
CCNH
/T
/T
/T
SMCCD
SMCCCS
SMWCC
Write
4
6
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
5.0/0.0
6.0/0.0
6.0/0.0
7.5/0.0
7.0/0.0
7.0/0.0
ds083-3_10_012004
Value
12.0
T
50
50
50
SMCCCS
T
SMWCC
MHz, max
MHz, max
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
39

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