TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 104

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
Read-
modify-
write
instructions
are
prohibited.
B0CS
(00C0H)
B1CS
(00C1H)
B2CS
(00C2H)
B3CS
(00C3H)
BEXCS
(00C7H)
0
1
0
1
Master enable bit
CS2 area selection
Disable
Enable
16-Mbyte area
Specified address area
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
B0E
B1E
B2E
B3E
W
W
W
7
0
0
1
0
Figure 3.6.5 Chip Select/Wait Control Registers
CS2 area
selection
0: 16-Mbyte
1: CS area
area
B2M
Chip Select/Wait Control Registers
6
0
Chip select output waveform
selection
00 For ROM/SRAM
01
10
11
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
11:
Don’t care
B0OM1
B1OM1
B2OM1
B3OM1
91C820A-102
5
0
0
0
0
Don’t care
Don’t care
Don’t care
Don’t care
B0OM0
B1OM0
B2OM0
B3OM0
4
0
0
0
0
W
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
Data bus
width
0: 16 bits
1: 8 bits
BEXBUS
B0BUS
B1BUS
B2BUS
B3BUS
3
0
0
0
0
0
W
W
W
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits
011: 0 waits
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits
011: 0 waits
0
1
Number of address area waits
BEXW2
(See 3.6.2 (3) “Wait control”.)
B0W2
B1W2
B2W2
B3W2
Data bus width selection
16-bit data bus
8-bit data bus
2
0
0
0
0
0
0
BEXW1
B0W1
B1W1
B2W1
B3W1
1
0
0
0
0
0
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
TMP91C820A
BEXW0
2008-02-20
B0W0
B1W0
B2W0
B3W0
0
0
0
0
0
0