TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 289

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Note 1: SDCLK is output in the IDLE2 mode. Therefore if you stop SDCLK, change PF6 pin to output port
Note 2: Pin condition under the IDLE1/STOP mode depends on the setting of SYSCR2<DRVE>. SDCKE
SDUDQM
SDLDQM
SDRAS
SDCAS
SDWE
SDCKE
SDCLK
SDCS
before the HALT instruction.
doesn’t depend on it but outputs low level.
which an internal clock stops. Before HALT instruction (STOP, IDLE1) of interval
refreshment in the state of enable, please set SDRCR<SFRC> to 1.
mode.
returns to the interval refreshment mode.
therefore, refresh is not performed.).
which sets 1 to SDRCR<SFRC>. After setting SDRCR<SFRC> to 1, make sure that the
HALT instruction comes after NOP or some instruction.
Self refresh
entry
If SDRCR<SFRC> is set to 1, the self-refresh cycle shown in Figure 3.16.9 will occur.
The self refreshment mode is used when using the standby mode (STOP, IDLE1)
Release of a self refresh cycle is automatically performed by release in the standby
It inserts automatically one interval refreshment after self refreshment release, and
(Note: When HALT instruction is cancelled by a reset, the I/O registers are initialized,
Please do not place the command which accesses SDRAM just before the command
Halt entry
Figure 3.16.9 Self Refresh Cycle
91C820A-287
Self-refresh cycle
Halt exit
Self refresh
exit
Auto
refresh
TMP91C820A
2008-02-20