TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 105

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(1) Master enable bits
(2) Data bus width selection
master bit, which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. Reset disables (Sets to 0) <B0E>,
<B1E> and <B3E>, and enabled (Sets to 1) <B2E>. This enables area CS2 only.
select/wait control register specifies the width of the data bus. This bit should be set to
0 when memory is to be accessed using a 16-bit data bus and to 1 when an 8-bit data
bus is to be used.
is known as dynamic bus sizing. For details of this bus operation see Table 3.6.2.
Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the
Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip
This process of changing the data bus width according to the address being accessed
91C820A-103
TMP91C820A
2008-02-20