TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 163

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

BR1ADD
(020BH)
(020CH)
BR1CR
0
1
+ (16 − K)/16 division enable
BR1ADD
<BR1K3:0>
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Disabled
Enabled
Note1:Availability of +(16-K)/16 division function
Note2:Set BR1CR <BR1ADDE> to 1 after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when +(16-K)/16 division
1111 (K = 15)
0001 (K = 1)
Figure 3.9.15 Baud Rate Generator Control (Channel 1, BR1CR, BR1ADD)
0000
to
function is used. Writes to unused bits in the BR1ADD register do not affext operation, and undefined data is
read from these unused bits.
BR1CR
<BR1S3:0>
Always
write “0”.
Baud rate generator frequency divisor setting
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function. Don’t use in
I/O interface mode.
N
2 to 15
1 , 16
7
−
0
7
+ (16 − K)/16
division
0: Disable
1: Enable
BR1ADDE
0000(N = 16)
0001(N = 1)
6
0
6
UART mode
Disable
Disable
BR1CR<BR1ADDE> = 1
or
○
×
00: φT0
01: φT2
10: φT8
11: φT32
00
01
10
11
BR1CK1
Input clock selection for baud rate generator
5
0
5
N + (16 − K)/16
91C820A-161
1111 (N = 15)
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
0010 (N = 2)
Disabled by
Disable
to
BR1CK0
I/O mode
4
4
0
×
×
R/W
BR1CR<BR1ADDE> = 0
0001(N = 1) (Only UART)
BR1K3
BR1S3
3
0
3
0
Setting of the divided frequency “N”
1111 (N = 15)
0000 (N = 16)
Divided by N
(Divided by N + (16 − K)/16)
Sets frequency divisor “K”
to
BR1S2
BR1K2
2
2
0
0
(0 to F)
R/W
BR1S1
BR1K1
1
1
0
0
BR1S0
BR1K0
TMP91C820A
0
0
0
0
2008-02-20